The present invention relates to manufacturing a semiconductor device, and more particularly, to a method of forming a mask layout using a fracturing process that is required for electron beam exposure or electron beam writing, and a mask layout formed by the same.
As the integration of a semiconductor device increases, the reduction in a design rule also occurs. As a result, the likelihood of distortion increases during the transfer of a pattern onto a photo mask due to a resolution restriction when using lithography to form the pattern. A resolution enhancement technology, such as optical proximity correction (OPC), has been proposed to overcome the resolution restriction of lithography.
Several attempts have been made to change the array of a device disposed on a wafer to increase the integration of the device. For example, a cell layout may be changed from an 8F2 cell layout to a 6F2cell layout or a 4F2 cell layout for a dynamic random access memory (DRAM) device.
According to the change of the cell layout, the shape of a pattern to be transferred onto a wafer has been changed into a diagonal pattern. For example, in the 6F2 layout, a pattern for a device isolation layer to form an active region does not extend in the horizontal direction perpendicular to a word line. Rather, the pattern extends diagonally to intersect a word line at an angle other than 90 degrees (e.g., an angle of approximately 27 degrees).
After the OPC process is performed on the layout having a diagonal pattern, it is necessary to perform an electron beam exposure process to transfer the layout onto a photo mask substrate. An extended time period may be required to perform the electron beam exposure process due to the shape of the electron beam.
FIG. 1 illustrates a conventional mask layout for a device isolation layer. FIG. 2 is an enlarged view of part C of FIG. 1. FIG. 3 illustrates the results of fracturing the mask layout of FIG. 1.
The cell layout illustrated in FIG. 1 may be a layout for a device isolation layer of a 6F2 cell in which a rectangle-shaped or polygon-shaped diagonal pattern 10 is arranged at an angle of approximately 27 degrees. The diagonal pattern 10 may be a layout to define an active region 13 and a device isolation region 14. The layout of the diagonal pattern 10 is represented by angle values representing the positions of vertices 15 of the polygon, which may be read by a computer aided design (CAD) system or an electron beam exposure system.
In the 6F2 cell layout, the diagonal pattern 10 extends at an angle of approximately 27 degrees (A) from the horizontal direction (X), which is a word line direction. The vertical direction (Y) is a bit line direction that is perpendicular to the horizontal direction (X). The diagonal pattern 10 is repeatedly arranged in the diagonal direction (A). In a subsequent process, fracturing is performed using this layout. The layout is then transferred onto a photo mask through electron beam exposure.
The 6F2 cell layout illustrated in FIG. 1 is a corrected layout obtained by the OPC process. The 6F2 cell layout includes a corrected pattern 16 having the shape of a serif polygon according to the OPC process. The corrected pattern 16 is merged with the diagonal pattern 10.
The corrected pattern 16 obtained by the OPC process has a shape in which a segment having a predetermined size is moved in the direction (B) perpendicular to a side 11 of the diagonal pattern 10. The direction (B) may be the same direction as an extension direction of an edge side 12 of the diagonal pattern 10. As illustrated in FIG. 2, vertices 17 are further provided by the merge of the corrected pattern 16 with the diagonal pattern 10. The corrected pattern 16 includes angle values representing the vertices 17.
An electron beam exposure process is performed when the layout of FIG. 1 with the above-described construction is transferred onto a photo mask. A vector-scan type electron beam exposure system, which uses a specific beam shape (e.g., a variable beam shape), can only expose a beam having a restricted shape (e.g., a rectangle or a trapezoid). The electron beam exposure system recognizes angle values of 0, 90, and 45 degrees that represent the rectangle or the trapezoid.
The layout data of FIG. 1 is converted into a data format that can be recognized by the electron beam exposure system. A fracturing process is performed to convert the layout into exposure elements related to the size of the exposed electron beam. FIG. 3 illustrates the results of fracturing the layout of FIG. 1.
Referring to FIG. 3, slivers 23 and 25, which are small-sized regions, may be undesirably generated between divided polygonal fractured regions 21 during the fracturing process. The silvers 23 and 25 are generated because the vertices 15 and 17 representing the diagonal pattern 10 and the corrected pattern 16 are represented by an angle value of 27 degrees. The only angle values that are recognized by the electron beam exposure system are 0, 45, and 90 degrees.
Generally, the fracturing direction is the horizontal direction (X). However, the vertices 15 and 17 each form an angle of predetermined size from the fracturing direction, for example 27 degrees. A plurality of slivers 23 are generated during the fracturing process in connection with the vertices 15 and 17.
The slivers 23 do not have a fractured region size, which is a relatively large size set by a user. Generally, the slivers 23 are automatically set to a minimum size allowed in the electron beam exposure system. The size of the slivers 23 is set to the minimum size allowable in a smaller-sized exposure system (e.g., 50 nm). The minimum size of the fractured region is set to a critical dimension of 100 nm.
The main fractured regions 21 are undesirably divided, and therefore slivers 25 may be generated between the divided fractured regions 21. When the fracturing process is performed on the corrected layout, a process is performed for enlarging (e.g., by 4 times) the CAD data of the corrected layout (FIG. 1). During a photolithography process (e.g., during a 1:4 reduction photolithography) a process for enlarging (e.g., by 4 times) layout data of FIG. 1 that is manufactured according to the design rule to be formed on a wafer using the CAD is required to perform the electron beam exposure on the photo mask.
Due to the vertices 17 generated when the corrected pattern 16 (FIG. 2) is merged with the diagonal pattern 10, undesirable vertices may be additionally generated at the side 11 of the diagonal pattern 10. These vertices may form a concave shape which may be generated when the diagonal pattern 10 is enlarged to a straight line. Enlarged layout data may include data from the additionally generated vertex. Due to the additional vertex data, the slivers 25 may be generated during the fracturing process as shown in FIG. 3.
The slivers 23 and 25 may be polygonal regions having a size much less than that of the main fractured regions 21. Specifically, the polygonal regions have the minimum size allowable in the electron beam exposure system. The generation of the slivers 23 and 25 may be a principal factor that greatly increases the number of electron beam exposure shots in a practical exposure process. The increase of the number of the electron beam exposure shots may be a factor that increases the time necessary for electron beam exposure (e.g., by at least a factor of 4). Photo mask pattern defectiveness (e.g., critical dimension defectiveness) may also be caused due to the degradation of a resist layer on which the electron beam exposure is performed.